Microelectronic devices arc typically formed from a semiconductor material, for example silicon, germanium, etc . . . . It has been a trend to increase the packaging density of wafers. The large integration of semiconductor ICs has been accomplished by a reduction in individual device size. With this reduction of device size, many challenges arise in the manufacture of the ICs. As semiconductor devices become more dense, it is also necessary to decrease the size of circuit components.
Modern integrated circuits interconnect literally millions of devices to perform a certain function. The performance of the integrated circuits is related to the performance and reliability of its constituent individual devices. In order to drive or control these devices to perform their function, periphery circuits are needed for the integrated circuits. Each device requires interconnections for exchanging electrical signals from one device to another device. Specifically, multi-level interconnection techniques are widely used for high density integrated circuits.
One prior art method for fabricating the interconnection is shown in FIG. 1, which shows a semiconductor substrate 2. Interconnections 4 are patterned over the substrate 2. A dielectric layer 6 such as an oxide is deposited over the semiconductor substrate 2 for isolation purposes. Then, a contact hole 8 is formed in the dielectric layer 6. The contact hole 8 is typically formed by using photolithography technologies. For high density integrated circuits, the dimension of the contact hole 8 must be made smaller. Indeed, the smaller the contact hole 8 the better. However, the width of the contact hole 8 is limited by the resolution of the photolithography techniques. Assume that the lowest width dimension of the contact hole 8 formed by current lithography technologies is represented by "W1" in FIG. 1. The space between the edge of the contact hole 8 and the underlying interconnections 4 is denoted by "S1".
The aforementioned structure is well known and widely used in the fabrication of ULSI (ultra large scale integrated) circuits. However, the general processes become more challenging as the spacing between the metal interconnections 4 further shrink. Further, reducing the size of conventional contact hole 8 is limited, due to the limits of photolithography. The spacer "S1" becomes smaller and smaller as the space between interconnections 4 becomes smaller. Therefore, the spacer dimension "S1" becomes so small that it is no longer reliable for insulation purposes. Thus, what is required is a method for making the contact hole 8 with reduced width dimension that is beyond the limitation of current photolithography techniques.
Isolation techniques, such as the local oxide of silicon (LOCOS), have been developed to isolate devices in integrated circuits. In the LOCOS approach, a silicon oxide/silicon nitride composition layer covers active regions of the wafer. The silicon oxide/silicon nitride composition structure serves as a mask for subsequent processing. Then, field oxide (FOX) isolations are formed on the unmasked regions by thermal oxidation in oxygen. However, at the edges of the silicon nitride, some oxidant laterally diffuses. Oxide forms under the nitride edges and lifts the nitride edges. This lateral extension of the field oxide into the active region of the wafer is known as the "bird's beak effect."
Many techniques have been developed in an attempt to reduce the undesirable encroachment of bird's beak. However, in the present invention, the extended bird's beak penetration effect can be used to reduce the size of the contact hole.